1. Field of the Invention
This invention relates generally to memory modules. In particular, the present invention relates to a memory module having its own clock generator.
2. Description of the Related Art
Some processing systems or functions in processing systems may have stringent memory processing requirements and thus utilize a type of memory module which is well suited to those processing requirements. One type of memory module specifically designed to have higher operating characteristics is a Rambus In-line Memory Module (xe2x80x9cRIMMxe2x80x9d), available for license from Rambus, Inc. of Mountain View, Calif. However, a RIMM has stringent interface and clocking signal requirements. Such requirements generally make the motherboards and other devices which support and interface with RIMMs more expensive than devices which support and interface with other types of memory modules.
FIG. 1 illustrates a conventional installation of a plurality of RIMM(trademark) memory modules. As shown, they are mounted on a number of packaging units 102-1, 102-2, etc., electrically coupled in daisy chain fashion to memory interface 104 via Rambus channel 103. RIMMs 102-1, etc. obviously differ from DIMMs insofar as they have a plurality of Rambus Dynamic Random Access Memory xe2x80x9cRDRAMxe2x80x9d (trademark) 101-1 rather than DRAM, but they also conventionally require two pins for every one of the signals, including clocking signals, on Rambus channel 103 so that they can be coupled in sequence in daisy chain fashion as shown in FIG. 1.
The daisy chain arrangement of RIMMs 102-1, etc., provides electrical performance advantages. But it also results in a different form factor (size, etc.) and clocking signal requirements. These clocking signal requirements necessitate that a Direct Rambus Clock Generator (DRCG) 105 (and all discrete components associated with DRCG 105 ) and clock termination topology 106 must be provided on motherboard 100. (Although FIG. 1 shows DRCG 105 on a motherboard, it may also be installed on another board even though only mother board 100 is discussed herein.) DRCG 105 and termination 106 require a significant amount of board space and thus impose significant layout constraints on mother board 100. In addition, because the signals must be terminated on motherboard 100, all the clock signals must return from each one of RIMMs 102-1, etc. to motherboard 100, thereby requiring two pins for every clocking signal on each one of RIMMs 102-1, etc.
The present invention is directed to a memory module having one or more memory devices, a clock generator providing clocking signals, and a clocking topology connecting the clocking signals to the memory device(s).